Digital logic can generally be characterized as either combinational circuits or sequential circuits. Combinational circuits are based on logic gates, and their outputs are directly determined by the present input values applied to the circuit. Combinational circuits perform operations that are logically specified by a series of Boolean expressions. Sequential circuits may also include logic gates, but additionally employ storage devices referred to as flip-flops. The outputs of storage devices depend not only on the present values of some inputs, but also on the previous values of some inputs. The operation of flip-flops in a sequential logic circuit is typically synchronized by a system clock. Thus the operation of sequential logic circuits is characterized by internal states as well as a time sequence of the inputs thereof.
Most digital systems include a blend of combinational and sequential logic circuits. Examples of storage devices used in sequential logic circuits utilizing flip-flops include latches, registers, counters, static memory arrays, and so forth. Since the operation of flip-flops affects the speed and power of the digital systems, it is very important to effectively design sequential logic circuits in order to achieve high-speed and low-power operation.
A recent trend in the design of digital systems involves the use of gated clock logic circuits to reduce the amount of power consumed by flip-flops. Gated clock logic circuits are structured to apply a clock signal to flip-flops in response to an enable signal only when the flip-flops need to operate, thereby reducing power consumption. An example of a conventional gated clock logic circuit is shown in FIG. 1. Referring to FIG. 1, a gated clock logic circuit 1 generates a gated clock signal GCK which is synchronized with a clock signal CK while a control signal (EN or TE) is active. The performance of the gated clock logic circuit 1 of FIG. 1 is determined by its EtoG time which is a delay time from an activation point of the enable signal (EN or TE) to an output point of the gated clock signal GCK. As shown in FIG. 1, the EtoG time is determined by a transmission path (illustrated as a dotted line in FIG. 1).